Stacked memory allowing variance in device interconnects

ABSTRACT

A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

TECHNICAL FIELD

Embodiments of the invention generally relate to the field of electronicdevices and, more particularly, to a stacked memory allowing variance indevice interconnects.

BACKGROUND

To provide memory with higher bandwidth for various kinds of computingoperations, memory devices having a plurality of closely coupled memoryelements (which may be referred to as 3D stacked memory, or stackedmemory) are being developed.

A 3D stacked memory may include coupled layers or packages of DRAM(dynamic random-access memory) memory elements, which may be referred toas a memory stack. Stacked memory may be utilized to provide a greatamount of computer memory in a single device or package, where thedevice or package may further include system components, such as amemory controller and CPU (central processing unit) or other systemelements.

However, stacked memory may require a large number of connections in asmall physical area. For this reason, the connections may be required tobe very small in size, thereby increasing cost and limiting flexibilityin manufacturing.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are illustrated by way of example, and notby way of limitation, in the figures of the accompanying drawings inwhich like reference numerals refer to similar elements.

FIG. 1 illustrates an embodiment of a 3D stacked memory;

FIG. 2 illustrates elements of an embodiment of a stacked memory device;

FIGS. 3A, 3B, and 4 illustrate connections for embodiments of a stackedmemory device having varying numbers of memory die layers;

FIG. 5 illustrates an embodiment of a pad layout for stacked memorydevices supporting varying pitch of interface connections; and

FIG. 6 is a block diagram to illustrate an embodiment of an apparatus orsystem including a stacked memory device.

DETAILED DESCRIPTION

Embodiments of the invention are generally directed to a stacked memorywith interface providing offset interconnects.

As used herein:

“3D stacked memory” (where 3D indicates three-dimensional) or “stackedmemory” means a computer memory including one or more coupled memory dielayers, memory packages, or other memory elements. The memory may bevertically stacked or horizontally (such as side-by-side) stacked, orotherwise contain memory elements that are coupled together. Inparticular, a stacked memory DRAM device or system may include a memorydevice having a plurality of DRAM die layers. A stacked memory devicemay also include system elements in the device, which may be referred toherein as a system layer or element, where the system layer may includeelements such as a CPU (central processing unit), a memory controller,and other related system elements. The system layer may include a logicchip or a system on chip (SoC).

In some embodiments, an architecture for a stacked memory deviceprovides for a die-to-die memory interface that support multipledifferent pad pitches depending on the number of memory layers in thestacked memory. In some embodiments, an architecture makes use of astructure of a stacked memory device, by which less than all possibleconnections pads are utilized when the stacked memory device has fewerthan a maximum number of memory layers in a memory stack.

The need for both increased memory bandwidth and increased memoryefficiency have has encouraged development of package memories usingvery wide interfaces. An example of this is the JEDEC WideIO memorystandard, which uses 1200 interconnects between the logic chip and thememory (which may generally be referred to as the logic memoryinterconnect, or LMI). These memory solutions may provide greater memorybandwidth efficiency in comparison with other low-power DRAMtechnologies such as LPDDR2 or LPDDR3 (Low Power Double Data Rate 2 and3).

To implement the wide interface with a moderate memory die size impact,fine pitch interfaces (such as 40 μm) may be required. The use of suchfine pitches necessitates using silicon-to-silicon connections, whereeither the memory is stacked directly on system element, thus requiringthe use of through silicon vias (TSVs) for the logic chip, or both thememory and the system are mounted on a silicon interposer. However,these arrangements suffer from increased cost requirements associatedwith the TSV processing of the system element or the inclusion of thesilicon interposer in the structure. The very fine pitch interfaces arenot compatible with mixed substrate materials, such as the coupling of asilicon die layer with an organic substrate of a system element.

In higher end systems, in order to obtain the required memory capacitywith in-package memories, memories stacked with TSVs may be employed inthe memory chips. However, this structure increases the cost per bit ofthe memories. In the example of the WideIO interface, the data lines arebuses, where each of the 512 data lines from one memory chip isconnected to a corresponding data line of the 512 data lines of allother memory chips, which are then connected with 512 data lines on thememory controller. However, this sharing of the data lines means thatthe bandwidth of the memory system remains the same regardless of howmany memory chips are stacked.

In some embodiments, a different approach for stacking memories utilizesdata lines that are not shared. As opposed to the connection of all datalines, while the data lines are passed through each of the memory dielayers in the memory stack, each memory die layer only drives a subset(such as one-quarter) of the data lines of the memory device. In thisapproach, the bandwidth of the memory stack increases as memory dielayers are added to the memory stack. In such a device implementation,the entire interface still has a large number of data lines requiringuse of fine pitch interconnect for a maximum stack of memory die layers,but each memory chip only drives a subset of the data lines.

The costs involved with developing a memory chip are substantial, andthe costs involved in stacking memory chips are also significant. Insome embodiments, a single memory design allows for serving lower end,single memory chip memory systems as well as higher end, multiple chipmemory systems. The cost per bit of a single memory die layer is lessexpensive than the cost of a multiple TSV stacked memory “cube” becauseof the additional processing and yield fall out of memory chip TSVprocessing and stacking. However, in conventional devices, a singlememory chip would still required to employ fine pitch interconnects,necessitating expensive TSV processing in the logic device or expensivesilicon interposers.

In some embodiments, a memory device utilizes an architecture allowingfor each memory chip to drive a subset (such as one-quarter) of the datalines, allowing for populating only a subset of the mechanicalconnections on the die using a top-level metal mask change and a changeto the DRAM wafer post processing. Because only a subset of the pads arerequired, in some embodiments organizing the pads of the memory chipyields a pad pitch that can be assembled using, for example,conventional C4 (Controlled Collapse Chip Connection, or Flip Chip)packaging techniques.

In some embodiments, a single memory specification and a single memorychip design may be utilized to support a range of applications. In highend implementations, memory wafers may be processed with an entire finepitch interface populated and with TSVs developed. The dies may then besingulated and assembled into memory stacks that expose the entire finepitch memory interface. These memory stacks are then stacked on a systemelement (logic chip) that is constructed utilizing TSVs. For spaceconstrained designs that need only a single DRAM chip's capacity, memorywafers may be processed and the entire fine pitch interface arraypopulated, but TSVs are not developed. The dies may then be singulatedand stacked on a logic chip that is built with TSVs. For cost sensitiveapplications, memory wafers may be processed, but with only a firstsubset of the interface array being populated and TSVs not beingdeveloped. The dies may then be singulated and assembled in a package,next to a logic chip, using, for example, conventional C4-type assemblytechniques.

In some embodiments, a memory device includes a system element for thememory device, the system element including multiple pads, and a memorystack connected with the system element, the memory stack having one ormore memory die layers, a connection of the system element and thememory stack including interconnects for connecting a first memory dielayer and the plurality of pads of the system element. For a singlememory die layer in the memory stack, a first subset of the plurality ofpads is utilized for a first group of interconnects for the connectionof the system element and the memory stack, and for two or more memorydie layers, the first subset and an additional second subset of theplurality of pads are utilized for the first group of interconnects anda second group of interconnects for the connection of the system elementand the memory stack. In some embodiments, the first subset of theplurality of pads are spaced such that at least one pad is locatedbetween each pad of the first subset of pads. In some embodiments, allof the pads of the plurality of pads are used for interconnects if thenumber of memory die layers is a maximum number of memory die layers forthe memory.

In some embodiments, a first pitch of interconnect is used for theinterconnects of the first memory die layer and the system element ifthe single memory die layer is the sole memory die layer in the memorystack, and a second pitch of interconnect is used for the interconnectsof the first memory die layer and the system element if a certain numberof memory die layers are present in the memory stack, the certain numberbeing two or greater, the first pitch of interconnect being greater thanthe second pitch of interconnect.

FIG. 1 illustrates an embodiment of a 3D stacked memory. In thisillustration, a 3D stacked memory device 100 includes a system element110 coupled with one or more DRAM memory die layers 120, also referredto herein as the memory stack. In some embodiments, the system elementmay be a system on chip (SoC) or other similar element. The elements ofthis figure and the following figures are presented for illustration,and are not drawn to scale. While FIG. 1 illustrates an implementationin which the system element 110 is coupled below the memory stack of oneor more memory die layers 120, embodiments are not limited to thisarrangement. For example, in some embodiments a system element 110 maybe located adjacent to the memory stack 120, and thus may be coupled ina side-by-side arrangement with the memory stack 120.

In this illustration, the DRAM memory die layers include four memory dielayers, these layers being a first memory die layer 130, a second memorydie layer 140, a third memory die layer 150, and a fourth memory dielayer 160. However, embodiments are not limited to any particular numberof memory die layers in the memory stack 110, and may include a greateror smaller number of memory die layers. Among other elements, the systemelement 110 may include a memory controller 112 for the memory stack120. In some embodiments, each memory die layer (with the possibleexception of the top, or outermost, memory die layer, such as the fourthmemory die layer 160 in this illustration) includes a plurality ofthrough silicon vias (TSVs) to provide paths through the siliconsubstrate of the memory die layers.

In some embodiments, each memory die layer includes an interface for aconnection with another die layer or the system element 110. In thisillustration, the first memory die layer 130 includes a first interface125 for the coupling between the first memory die layer 130 and thesystem element 110; the second memory die layer 140 includes a secondinterface 135 for the coupling between the second memory die layer 140and the first memory die layer 130; the third memory die layer 150includes a third interface 145 for the coupling between the third memorydie layer 150 and the second memory die layer 140; and the fourth memorydie layer 160 includes a fourth interface 155 for the coupling betweenthe fourth memory die layer 160 and the third memory die layer 150.

In some embodiments, the stacked memory device 100 is structured suchthat each memory die drives a subset of the logic memory interconnect,and the structure is utilized to allow for variation in pitch forinterconnects between the memory stack and the system element 110. Insome embodiments, the stacked memory device 100 provides forinterconnect pad placement that are spaced to allow for variation inpitch of interconnects with variation in a number of memory die layersin the memory stack.

FIG. 2 illustrates elements of an embodiment of a stacked memory device.In some embodiments, a stacked memory device 200 includes a memory stack215, where the memory stack in this illustration has four memory dielayers, a first memory die layer 220, a second memory die layer 230, athird memory die layer 240, and a fourth memory die layer 250. In thisillustration, the memory stack is coupled to a system element 210 (whichmay also be referred to as a logic chip), which may be a system on chipor similar element. While the memory stack is shown coupled directlywith the system element 210, in other implementations the elements maybe coupled in a different manner, where, for example, both the memorystack 215 and the system element 210 may be coupled with a siliconinterposer between the memory stack and the system element 210.

As shown in FIG. 2, the memory die layers 215 may include throughsilicon vias 235 to provide signal paths through the memory die layersand interfaces between the memory die layers 215, or between a memorydie layer 220 and the system element 210.

In some embodiments, the stacked memory device 200 is structured suchthat each memory die drives a subset of the logic memory interconnect,and the structure is utilized to allow for variation in pitch forinterconnects between the memory stack and the system element 210. Inthis illustration providing four memory die layers, the device 200 maybe structured such that each memory die layer drives one-quarter of thememory interconnect. In some embodiments, the stacked memory device 200provides for interconnect pad placement that are spaced to allow forvariation in pitch of interconnects with variation in a number of memorydie layers in the memory stack.

FIGS. 3A, 3B, and 4 illustrate connections for an embodiment of astacked memory device having varying numbers of memory die layers. Inthe illustration provided in FIG. 3A, a stacked memory device 300includes a memory stack 315, where the memory stack in this illustrationhas four memory die layers, a first memory die layer 320, a secondmemory die layer 330, a third memory die layer 340, and a fourth memorydie layer 350. In this illustration, the memory stack is coupled to asystem element 310 by a full number of fine interconnects 370 becausesufficient memory die layers are included in the memory stack 315 torequire the maximum number of interconnects for the device 300. In someembodiments, the device architecture allows for full memory for highpower operations in the configuration shown in FIG. 3A. In someembodiments, the interconnects 370 utilize a pad layout architecture(such as, for example, the pad layout illustrated in FIG. 5) providingspacing between pads required for a smaller memory die to allow forvariation in interconnect pitch as the number of memory die layers in amemory stack is varied.

In the illustration provided in FIG. 3B, a stacked memory device 302includes a memory stack 317 and system element 312 connected via apackage substrate 380, where the package substrate may be, for example,a silicon interposer 382 coupled with a non-silicon substrate 384, or asilicon substrate (not illustrated here). In this illustration, thememory stack 317 again includes four memory die layers, a first memorydie layer 322, a second memory die layer 332, a third memory die layer342, and a fourth memory die layer 352. In this illustration, the memorystack 317 and the system element 312 are connected with the substrate380 by the full number of fine interconnects 372 because againsufficient memory die layers are included in the memory stack 317 torequire the maximum number of interconnects for the device 302. In someembodiments, this alternative device architecture may also provide forfull memory for high power operations, and interconnects 372 and 374 forthe coupling of the memory stack 317 and system element 312 to thesilicon interposer 382 or silicon substrate may utilize a pad layoutarchitecture providing spacing between pads required for a smallermemory die to allow for variation in interconnect pitch as the number ofmemory die layers in a memory stack is varied.

In contrast, FIG. 4 illustrates connections for an embodiment of astacked memory device having a single memory die layer. In thisillustration, a stacked memory device 400 includes a memory die layer422 connected with a system element 412 through a non-silicon packagesubstrate 484, such as an organic substrate. Embodiments are not limitedto this arrangement, and a face of the single memory die layer 422 mayalso be coupled with a face of the system element 410 in a similarmanner to FIG. 3A, or connected using a silicon interposer asillustrated in FIG. 3B. However, the implementation illustrated in FIG.4 may provide additional cost savings in manufacture. In someembodiments, the stacked memory device 400 includes the memory die layer422 and the system element 412 coupled to the non-silicon substrate 484by a reduced number of regular pitch interconnects, interconnects 472and 474 respectively (wherein such interconnects are thicker than thefine pitch interconnects illustrated in FIGS. 3A and 3B) because asingle memory die layer requires only a subset of the maximum number ofinterconnects for the device 400. In some embodiments, the interconnects472 and 474 again utilize a pad layout architecture (such as, forexample, the pad layout illustrated in FIG. 5) providing spacing betweenpads required for a smaller number of memory die to allow for variationin interconnect pitch as the number of memory die layers in a memorystack is varied.

In some embodiments, the device architecture illustrated in FIGS. 3A,3B, and 4 allows both for memory at a lower cost (with cheaper packagingcosts), and for memory used in high power operations.

FIG. 5 illustrates an embodiment of a pad layout for stacked memorydevices supporting varying pitch of interface connections. In someembodiments, a memory device includes a pad layout 500 for a stackedmemory device that provides for spacing between connections to allow forvarying pitch interconnections depending on the number of memory dielayers in the device. The varying numbers of memory die layers may be,for example, as illustrated in FIGS. 3A, 3B, and 4.

In some embodiments, the pad layout 500 may include the connectionsrequired for memory operation, including data connection (DQ0 through DQ4) and power connections (VSS, VSS Q, VDD Q, and VDD 2 in thisillustration). In some embodiments, each memory die layer drives asubset of the memory interconnect of the device, thus allowing for areduction in the number of interconnects if there is reduction in thenumber of memory die layers. In some embodiments, the pad layout isstructured so that the active pads required for interconnection of asingle memory die device (which are, for example, the shaded pads 510 inFIG. 5) are spaced a minimum of one pad width in each direction. In someembodiments, the pad layout architecture 500 allows for a firstinterconnect pitch for connection of a larger number of memory dielayers (such as a maximum number of memory die layers requiring all ofthe pads of the pad layout architecture 500) and for a secondinterconnect pitch for a partial pad layout of the pads 510 required forfew memory die layers, such as a single memory die layer.

A stacked memory may be utilized in many different computingenvironments, depending on the number of memory die layers in a memorydevice. FIG. 6 is a block diagram to illustrate an embodiment of anapparatus or system including a stacked memory device. Computing device600 represents a computing device including a mobile computing device,such as a laptop, a computing tablet, a mobile phone or smartphone, awireless-enabled e-reader, or other wireless mobile device. It will beunderstood that certain of the components are shown generally, and notall components of such a device are shown in device 600. The componentsmay be connected by one or more buses or other connections 605.

Device 600 includes processor 610, which performs the primary processingoperations of device 600. Processor 610 can include one or more physicaldevices, such as microprocessors, application processors,microcontrollers, programmable logic devices, or other processing means.The processing operations performed by processor 610 include theexecution of an operating platform or operating system on whichapplications, device functions, or both are executed. The processingoperations include operations related to I/O (input/output) with a humanuser or with other devices, operations related to power management,operations, or both related to connecting device 600 to another device.The processing operations may also include operations related to audioI/O, display I/O, or both.

In one embodiment, device 600 includes audio subsystem 620, whichrepresents hardware (such as audio hardware and audio circuits) andsoftware (such as drivers and codecs) components associated withproviding audio functions to the computing device. Audio functions caninclude speaker, headphone, or both such audio output, as well asmicrophone input. Devices for such functions can be integrated intodevice 600, or connected to device 600. In one embodiment, a userinteracts with device 600 by providing audio commands that are receivedand processed by processor 610.

Display subsystem 630 represents hardware (such as display devices) andsoftware (such as drivers) components that provide a display havingvisual, tactile, or both elements for a user to interact with thecomputing device. Display subsystem 630 includes display interface 632,which includes the particular screen or hardware device used to providea display to a user. In one embodiment, display interface 632 includeslogic separate from processor 610 to perform at least some processingrelated to the display. In one embodiment, display subsystem 630includes a touchscreen device that provides both output and input to auser.

I/O controller 640 represents hardware devices and software componentsrelated to interaction with a user. I/O controller 640 can operate tomanage hardware that is part of audio subsystem 620, a display subsystem630, or both such subsystems. Additionally, I/O controller 640illustrates a connection point for additional devices that connect todevice 600 through which a user might interact with the system. Forexample, devices that can be attached to device 600 might includemicrophone devices, speaker or stereo systems, video systems or otherdisplay device, keyboard or keypad devices, or other I/O devices for usewith specific applications such as card readers or other devices.

As mentioned above, I/O controller 640 may interact with audio subsystem620, display subsystem 630, or both such subsystems. For example, inputthrough a microphone or other audio device can provide input or commandsfor one or more applications or functions of device 600. Additionally,audio output can be provided instead of or in addition to displayoutput. In another example, if display subsystem includes a touchscreen,the display device also acts as an input device, which can be at leastpartially managed by I/O controller 640. There can also be additionalbuttons or switches on device 600 to provide I/O functions managed byI/O controller 640.

In one embodiment, I/O controller 640 manages devices such asaccelerometers, cameras, light sensors or other environmental sensors,or other hardware that can be included in device 600. The input can bepart of direct user interaction, as well as providing environmentalinput to the system to influence its operations (such as filtering fornoise, adjusting displays for brightness detection, applying a flash fora camera, or other features).

In one embodiment, device 600 includes power management 650 that managesbattery power usage, charging of the battery, and features related topower saving operation.

In some embodiments, memory subsystem 660 includes memory devices forstoring information in device 600. The processor 610 may read and writedata to elements of the memory subsystem 660. Memory can includenonvolatile (having a state that does not change if power to the memorydevice is interrupted), volatile (having a state that is indeterminateif power to the memory device is interrupted) memory devices, or bothsuch memories. Memory 660 can store application data, user data, music,photos, documents, or other data, as well as system data (whetherlong-term or temporary) related to the execution of the applications andfunctions of system 600.

In some embodiments, the memory subsystem 660 may include a stackedmemory device 662, such as illustrated in FIGS. 1 through 5, where thestacked memory device includes one or more memory die layers and asystem element. In some embodiments, the stacked memory device 662provides for varying interconnects based on a number of memory dielayers, allowing for use of wider pitch interconnects in devicesutilizing a smaller number of memory dies.

Connectivity 670 includes hardware devices (e.g., connectors andcommunication hardware for wireless communication, wired communication,or both) and software components (e.g., drivers, protocol stacks) toenable device 600 to communicate with external devices. The device couldbe separate devices, such as other computing devices, wireless accesspoints or base stations, as well as peripherals such as headsets,printers, or other devices.

Connectivity 670 can include multiple different types of connectivity.To generalize, device 600 is illustrated with cellular connectivity 672and wireless connectivity 674. Cellular connectivity 672 refersgenerally to cellular network connectivity provided by wirelesscarriers, such as provided via GSM (global system for mobilecommunications) or variations or derivatives, CDMA (code divisionmultiple access) or variations or derivatives, TDM (time divisionmultiplexing) or variations or derivatives, or other cellular servicestandards. Wireless connectivity 674 refers to wireless connectivitythat is not cellular, and can include personal area networks (such asBluetooth), local area networks (such as WiFi), wide area networks (suchas WiMax), and other wireless communications.

Peripheral connections 680 include hardware interfaces and connectors,as well as software components (e.g., drivers, protocol stacks) to makeperipheral connections. It will be understood that device 600 could bothbe a peripheral device (“to” 682) to other computing devices, as well ashave peripheral devices (“from” 684) connected to it. Device 600commonly has a “docking” connector to connect to other computing devicesfor purposes such as managing (such as downloading, uploading, changing,or synchronizing) content on device 600. Additionally, a dockingconnector can allow device 600 to connect to certain peripherals thatallow device 600 to control content output, for example, to audiovisualor other systems.

In addition to a proprietary docking connector or other proprietaryconnection hardware, device 600 can make peripheral connections 680 viacommon or standards-based connectors. Common types can include aUniversal Serial Bus (USB) connector (which can include any of a numberof different hardware interfaces), DisplayPort including MiniDisplayPort(MDP), High Definition Multimedia Interface (HDMI), Firewire, or othertype.

In the description above, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. It will be apparent, however, toone skilled in the art that the present invention may be practicedwithout some of these specific details. In other instances, well-knownstructures and devices are shown in block diagram form. There may beintermediate structure between illustrated components. The componentsdescribed or illustrated herein may have additional inputs or outputswhich are not illustrated or described.

Various embodiments may include various processes. These processes maybe performed by hardware components or may be embodied in computerprogram or machine-executable instructions, which may be used to cause ageneral-purpose or special-purpose processor or logic circuitsprogrammed with the instructions to perform the processes.Alternatively, the processes may be performed by a combination ofhardware and software.

Portions of various embodiments may be provided as a computer programproduct, which may include a non-transitory computer-readable storagemedium having stored thereon computer program instructions, which may beused to program a computer (or other electronic devices) for executionby one or more processors to perform a process according to certainembodiments. The computer-readable medium may include, but is notlimited to, floppy diskettes, optical disks, compact disk read-onlymemory (CD-ROM), and magneto-optical disks, read-only memory (ROM),random access memory (RAM), erasable programmable read-only memory(EPROM), electrically-erasable programmable read-only memory (EEPROM),magnet or optical cards, flash memory, or other type ofcomputer-readable medium suitable for storing electronic instructions.Moreover, embodiments may also be downloaded as a computer programproduct, wherein the program may be transferred from a remote computerto a requesting computer.

Many of the methods are described in their most basic form, butprocesses can be added to or deleted from any of the methods andinformation can be added or subtracted from any of the describedmessages without departing from the basic scope of the presentinvention. It will be apparent to those skilled in the art that manyfurther modifications and adaptations can be made. The particularembodiments are not provided to limit the invention but to illustrateit. The scope of the embodiments of the present invention is not to bedetermined by the specific examples provided above but only by theclaims below.

If it is said that an element “A” is coupled to or with element “B,”element A may be directly coupled to element B or be indirectly coupledthrough, for example, element C. When the specification or claims statethat a component, feature, structure, process, or characteristic A“causes” a component, feature, structure, process, or characteristic B,it means that “A” is at least a partial cause of “B” but that there mayalso be at least one other component, feature, structure, process, orcharacteristic that assists in causing “B.” If the specificationindicates that a component, feature, structure, process, orcharacteristic “may”, “might”, or “could” be included, that particularcomponent, feature, structure, process, or characteristic is notrequired to be included. If the specification or claim refers to “a” or“an” element, this does not mean there is only one of the describedelements.

An embodiment is an implementation or example of the present invention.Reference in the specification to “an embodiment,” “one embodiment,”“some embodiments,” or “other embodiments” means that a particularfeature, structure, or characteristic described in connection with theembodiments is included in at least some embodiments, but notnecessarily all embodiments. The various appearances of “an embodiment,”“one embodiment,” or “some embodiments” are not necessarily allreferring to the same embodiments. It should be appreciated that in theforegoing description of exemplary embodiments of the present invention,various features are sometimes grouped together in a single embodiment,figure, or description thereof for the purpose of streamlining thedisclosure and aiding in the understanding of one or more of the variousinventive aspects. This method of disclosure, however, is not to beinterpreted as reflecting an intention that the claimed inventionrequires more features than are expressly recited in each claim. Rather,as the following claims reflect, inventive aspects lie in less than allfeatures of a single foregoing disclosed embodiment. Thus, the claimsare hereby expressly incorporated into this description, with each claimstanding on its own as a separate embodiment of this invention.

What is claimed is:
 1. A memory device comprising: a system element forthe memory device, the system element including a plurality of pads; anda memory stack connected with the system element, the memory stackincluding one or more memory die layers, a connection of the systemelement and the memory stack including a plurality of interconnects forconnecting a first memory die layer and the plurality of pads of thesystem element; wherein for a single memory die layer in the memorystack, a first subset of the plurality of pads is utilized for a firstgroup of interconnects for the connection of the system element and thememory stack, wherein the first subset of the plurality of pads arespaced such that at least one pad is located between each pad of thefirst subset of pads; and wherein for two or more memory die layers inthe memory stack, the first subset and an additional second subset ofthe plurality of pads are utilized for the first group of interconnectsand a second group of interconnects for the connection of the systemelement and the memory stack.
 2. The memory device of claim 1, whereinthe single memory die layer is the sole memory die layer in the memorystack, and wherein a first pitch of interconnect is used for theinterconnects of the first memory die layer and the system element. 3.The memory device of claim 1, wherein two or more memory die layers arepresent in the memory stack and wherein a second pitch of interconnectis used for the interconnects of the first memory die layer and thesystem element, a first pitch of interconnect used for a sole memory dielayer being greater than the second pitch of interconnect.
 4. The memorydevice of claim 1, wherein the memory device is structured for a subsetof a total logic memory interconnect between the memory stack and thesystem element of the memory device to be driven from each memory dielayer.
 5. The memory device of claim 1, wherein the number of memory dielayers is a maximum number of memory die layers for the memory stack,and wherein all of the pads of the plurality of pads are used forinterconnects.
 6. The memory device of claim 1, wherein the systemelement is a system on chip (SoC).
 7. A system comprising: a bus; astacked memory device coupled to the bus; and a processor coupled to thebus, the processor to read data from and write data to the stackedmemory device; wherein the stacked memory device includes: a systemelement for the stacked memory device, the system element including aplurality of pads, and a memory stack connected with the system element,the memory stack including one or more memory die layers, a connectionof the system element and the memory stack including a plurality ofinterconnects for connecting a first memory die layer and the pluralityof pads of the system element; wherein for a single memory die layer inthe memory stack, a first subset of the plurality of pads is utilizedfor a first group of interconnects for the connection of the systemelement and the memory stack, wherein the first subset of the pluralityof pads are spaced such that at least one pad is located between eachpad of the first subset of pads; and wherein for two or more memory dielayers in the memory stack, the first subset and an additional secondsubset of the plurality of pads are utilized for the first group ofinterconnects and a second group of interconnects for the connection ofthe system element and the memory stack.
 8. The system of claim 7,wherein the single memory die layer is the sole memory die layer in thememory stack, and wherein a first pitch of interconnect is used for theinterconnects between the first memory die layer and the system element.9. The system of claim 7, wherein two or more die layers are present inthe memory stack and wherein a second pitch of interconnect is used forthe interconnects if a certain number of memory die layers are presentin the memory stack, the certain number being two or greater, a firstpitch of interconnect used for a sole memory die layer being greaterthan the second pitch of interconnect.
 10. The system of claim 7,wherein the memory device is structured for a subset of a total logicmemory interconnect between the memory stack and the system element ofthe memory device to be driven from each memory die layer.
 11. A memorydevice comprising: a system element for the memory device, the systemelement including a plurality of pads; a memory stack connected with thesystem element, the memory stack including one or more memory dielayers, a connection of the system element and the memory stackincluding a plurality of interconnects for connecting a first memory dielayer and the plurality of pads of the system element; and a siliconinterposer, the connection including a coupling of the system elementand memory stack to the silicon interposer; wherein for a single memorydie layer in the memory stack, a first subset of the plurality of padsis utilized for a first group of interconnects for the connection of thesystem element and the memory stack; and wherein for two or more memorydie layers in the memory stack, the first subset and an additionalsecond subset of the plurality of pads are utilized for the first groupof interconnects and a second group of interconnects for the connectionof the system element and the memory stack.
 12. A memory devicecomprising: a system element for the memory device, the system elementincluding a plurality of pads; a memory stack connected with the systemelement, the memory stack including one or more memory die layers, aconnection of the system element and the memory stack including aplurality of interconnects for connecting a first memory die layer andthe plurality of pads of the system element; and a non-silicon packagesubstrate, the memory stack including a single memory die layer, and theconnection including a coupling of the system element and the singlememory die layer to the non-silicon package substrate; wherein for asingle memory die layer in the memory stack, a first subset of theplurality of pads is utilized for a first group of interconnects for theconnection of the system element and the memory stack; and wherein fortwo or more memory die layers in the memory stack, the first subset andan additional second subset of the plurality of pads are utilized forthe first group of interconnects and a second group of interconnects forthe connection of the system element and the memory stack.